TY  - BOOK
AU  - Shanley, T.
AU  - Anderson, Don
TI  - ISA system architecture
SN  - 0 201 40996 8
U1  - 004.324/S47 
PY  - 1995///
CY  - Massachusetts
PB  - Addison-Wesley Pub.
KW  - COMPUTADORAS
KW  - DISEÑO DE SISTEMAS
KW  - MICROPROCESADOR
N1  - Incluye índice: páginas 509-517; 1. Intro to microprocessor communications -- 2. Introduction to the Bus Cycle -- 3. Addressing I/O and memory -- 4. The address decode logic -- 5. The 80286 microprocessor -- 6. The reset logic -- 7. The power-up sequence -- 8. The 80286 system Kernel: the engine -- 9. Detailed view of the 80286 bus cycle -- 10. The 80386 DX and SX microprocessors -- 11. The 80386 system Kernel -- 12. Detailed view of the 80386 Bus cycles
ER  -